455A Datasheet, PDF (52/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

455A Group
(4) Internal state at reset
Figure 51 and 52 shows internal state at reset (they are the same
after system is released from reset). The contents of timers,
registers, flags and RAM except shown in Figure 51 and 52 are
undefined, so set the initial value to them.
• Program counter (PC)
Address 0 in page 0 is set to program counter.
• Interrupt enable flag (INTE)
• Power down flag (P)
• External 0 interrupt request flag (EXF0)
• Interrupt control register V1
• Interrupt control register V2
• Interrupt control register I1
• Timer 1 interrupt request flag (T1F)
• Timer 2 interrupt request flag (T2F)
• Timer 3 interrupt request flag (T3F)
• Watchdog timer flags (WDF1, WDF2)
• Watchdog timer enable flag (WEF)
• Timer control register PA
• Timer control register W1
• Timer control register W2
•Timer control register W3
• Timer control register W4
• Timer control register W5
• Clock control register MR
• Clock control register RG
• LCD control register L1
• LCD control register L2
• LCD control register L3
• LCD control register C1
• LCD control register C2
• LCD control register C3
Fig 51. Internal state at reset (1)
00000000000000
0 ^{(Interrupt disabled)}
0
0
0 0 0 0 ^{(Interrupt disabled)}
0 0 0 0 ^{(Interrupt disabled)}
0000
0
0
0
0
1
0 ^{(Prescaler stopped)}
0 0 0 0 ^{(Timer 1 stopped)}
0 0 0 0 ^{(Timer 2 stopped)}
0 0 0 0 ^{(Timer 3 stopped)}
0 0 0 0 ^{(Timer LC stopped)}
0000
1100
1000
0000
0000
1111
1111
1111
1111
Rev.1.01 Feb 15, 2008 Page 52 of 146
REJ03B0224-0101