455A Datasheet, PDF (145/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

455A Group
Voltage drop detection circuit characteristics
Table 35 Voltage drop detection circuit characteristics (Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Unit
Min.
Typ.
Max.
VRST-
Detection voltage
(reset occurs) (Note 1)
Ta = 25°C
−20°C≤ Ta < 0°C
1.7
V
1.6
2.2
0°C≤ Ta < 50°C
1.3
2.1
50°C≤ Ta ≤ 85°C
1.1
1.8
VRST+
Detection voltage
(reset release) (Note 2)
Ta = 25°C
−20°C≤ Ta < 0°C
1.8
V
1.7
2.3
0°C≤ Ta < 50°C
1.4
2.2
50°C≤ Ta ≤ 85°C
1.2
1.9
VSKIP
Detection voltage
(skip occurs) (Note 3)
Ta = 25°C
−20°C≤ Ta < 0°C
2
V
1.9
2.5
0°C≤ Ta < 50°C
1.6
2.4
50°C≤ Ta ≤ 85°C
1.4
2.1
VRST+ −VRST- Detection voltage hysteresis
0.1
V
IRST
Operation current (Note 4)
VDD = 5V
30
60
µA
VDD = 3V
15
30
VDD = 1.8V
6
12
TRST
Detection time (Note 5)
VDD → (VRST- −0.1V)
0.2
1.2
ms
Note 1. The detection voltage (VRST−) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling.
Note 2. The detection voltage (VRST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset
occurs.
Note 3. When the supply voltage goes lower than the detection voltage (VSKIP), the voltage drop detection circuit interrupt request flag
(VDF) is set to “1“.
Note 4. Voltage drop detection circuit operation current (IRST) is added to IDD (power current) when voltage drop detection circuit is used.
Note 5. The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST- −0.1V].
Basic timing diagram
Machine cycle
Mi
Parameter
Pin name
System clock
STCK
Mi + 1
Port output
Port input
Interrupt input
D0 to D7
P00 to P03
P10 to P13
P20 to P23
P30 to P33, C
D0 to D7
P00 to P03
P10 to P13
P20 to P23
P30 to P33
INT
Rev.1.01 Feb 15, 2008 Page 145 of 146
REJ03B0224-0101