R-IN32M3 Datasheet, PDF (79/116 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
(b) Write timing
4. Electrical Specifications
BUSCLK (output)
< t_DKA >
A1-A26 (output)
< t_DKA >
CSZ0-CSZ3 (output)
< t_DKWR >
WRZ0-WRZ3^note, WRSTB (output)
< t_DKWR >
BENZ0-BENZ3^note (output)
< t_DKA >
< t_DKWR >
< t_DKWR >
RDZ (output)
< t_DKOD >
< t_HKOD >
D0-D31 (i/o)
WAITZ (input)
< t_HKW >
< t_SKW >
< t_DKBS > ^{< tDKBS >}
BCYSTZ (input)
< t_DKOD >
Figure 4.5 Memory Controller Read Timing Diagram (Asynchronous Memory)
Note: The WRZ0-WRZ3 pins function both as WRZ0-WRZ3 and BENZ0-BENZ3. These pins function as
BENZ0-BENZ3 after a reset and can be switched with the write enable switch registers (WREN).
For details, see section 9.3.5, Write Enable Switch Registers (WREN), in the R-IN32M3 Series
User’s Manual: Peripheral Modules.
Remark: Above timing shows the case for when “Idle Wait”, “Write Recovery Wait”, and “Address
Wait” are set to 0, and “Data Wait” is set to 3.
R18DS0008EJ0401
Feb 28, 2017
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