R-IN32M3 Datasheet, PDF (61/116 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
3. Specifications
3.16 Synchronous Burst Access Memory Controller
The synchronous burst access memory controller can be used to connect external page ROM, ROM, SRAM, PSRAM,
NOR-Flash, and peripheral devices with an interface similar to the SRAM interface via the 32/16-bit bus.
By setting the ADMUXMODE pin to high level, the address signals can be multiplexed to be output from data pins.
The synchronous burst access memory controller and asynchronous SRAM memory controller share external
microcontroller interface pins. Using these pins for the synchronous burst access memory controller is selected when the
MEMCSEL pin outputs a high level and the MEMIFSEL pin outputs a low level.
The CPU is booted from the memory connected to CSZ0 when the BOOT0 pin outputs a low level and the BOOT1 pin
outputs a high level.
3.16.1 Features
- Memory controller supporting page ROM, ROM, SRAM (synchronous /asynchronous), PSRAM and NOR-Flash
- 32- or 16-bit data bus
- Address / data multiplex feature
Remark: Page access is possible only when performing asynchronous access in separate bus mode.
- Static memory control
 External connection of SRAM (synchronous, asynchronous) and other peripheral devices with an interface
similar to the SRAM interface
 Four chip select signals are available (CSZ0-CSZ3)
CSZ0: 1000 0000H-13FF_FFFFH (64 Mbytes)
CSZ1: 1400 0000H-17FF_FFFFH (64 Mbytes)
CSZ2: 1800 0000H-1BFF_FFFFH (64 Mbytes)
CSZ3: 1C00 0000H-1FFF_FFFFH (64 Mbytes)
Remark: Chip select areas can be assigned to the area between addresses 1000_0000H -
1FFF_FFFFH by using the SMADSEL register (specified in 16-MB units).
- Programmable wait
- Memory access frequency (by dividing 100 MHz signal by 2 to 6 )
- Up to four wait state signals available (WAITZ, WAITZ1 to WAITZ3) <R>
R18DS0008EJ0401
Feb 28, 2017
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