R-IN32M3 Datasheet, PDF (48/116 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
3. Specifications
3.5 General DMA Controller
3.5.1
Features
- Number of channels: 4 independent channels
- Transfer data size
 Independently selectable for source and destination
 Size range: 8 to 512 bits
- Maximum number of transfer bytes: 2³²-1
- Channel priority control
 Fixed priority mode
 Round robin mode (The channel that last completed a transfer is shifted to the lowest priority position.)
- DMA transfer methods
The data used for DMA transfer is set in an internal register by using the following two modes.
 Register mode:
DMA transfer is performed using the values set in the control registers of the DMA controller written by the CPU.
This mode supports conventional general DMA transfer.
 Link mode:
DMA transfer is performed according to a descriptor located in data RAM and external memory. The
responsiveness of this mode is inferior to register mode because access of the descriptor occurs at every DMA
transfer.
- Skip function
Continuous access size and discrete access size can each be set for the areas that are accessed with DMA transfer.
Following access of the set size, it is possible to skip to the next address to be accessed.
- Buffer data dump function
Then DMA is forced to stop, the function can dump the data stored in the buffer. After the dump, the DMA transfer is
continued.
- Suspension function
The ongoing DMA transaction can be suspended.
- DMA transfers interval setting function
The DMA transfer interval can be specified to adjust the bus occupancy rate.
- Transfer mode
 Single transfer mode
When a DMA transfer request is made, the right to use the bus is acquired and the bus is released each time a
transfer is completed. After that, whenever a DMA transfer request is made, this operation is repeated until the
numbers of transfers specified in the control register are completed.
 Block transfer mode
When a DMA transfer request is made, the right to use the bus is acquired and data transfer is repeated until the
numbers of transfers specified in the control register are completed. In this case, the bus is not occupied.
Caution: Transfer 512-bit wide data requires the data to be aligned on a 512-bit boundary.
R18DS0008EJ0401
Feb 28, 2017
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