R-IN32M3 Datasheet, PDF (29/116 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
2. Pin Information
2.3.14 CC-Link IE Field Pins (Intelligent Device Station) (R-IN32M3-CL only)
Pin Name
I/O
CCI_RUNLEDZ
O
CCI_DLINKLEDZ O
CCI_ERRLEDZ
O
CCI_LERR1LEDZ O
CCI_LERR2LEDZ O
CCI_SDLEDZ
O
CCI_RDLEDZ
O
CCI_NMIZ
O
CCI_WDTIZ
I
CCI_WAITEDGEH I/O
Note
CCI_WRLENH
I/O
Note
CCI_PHYREZ1
O
CCI_PHYREZ0
O
CCI_INTZ
O
CCI_CLK2_097M I
Function
RUN status output
Cyclic communication status output
Field network error status output
Link error status output 1
Link error status output 2
Transmission state output
Port reception state output
Output NMI interrupt to MCU
Input from external watchdog timer
Wait synchronized edge setting
0: Fall edge mode
1: Rise edge mode
WRL signal enable setting
0: Write byte enable mode
1: Normal byte enable mode
PHY reset output 1
PHY reset output 0
Output Interrupt to MCU
2.097152-MHz clock (crystal oscillator)
Shared
Port
P00
P02
P03
P04
P05
P06
P07
P12
P13
P33
Active
Low
Low
Low
Low
Low
Low
Low
Low
Low
-
P34
-
P56
Low
P57
Low
P66
Low
-
-
Level during Reset
Hi-Z (High)
Hi-Z (High)
-
Note: When user does boot with the external memory boot mode, external serial flash ROM boot
mode, or instruction RAM boot mode, be sure not to input the low level to P33 (multiplexed
with CCI_WAITEDGEH) and P34 (multiplexed with CCI_WRLENH) pins during a reset.
P33 and P34 pins should be left open circuit or the high level should be input to the pins during
a reset. If you input the low level to P33 and P34 pins during a reset, you cannot access the
CC-Link IE field from the CPU of the R-IN32M3.
R18DS0008EJ0401
Feb 28, 2017
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