R-IN32M3 Datasheet, PDF (63/116 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
3. Specifications
3.18 Data RAM
The internal data RAM is a 512-Kbyte RAM that can be accessed from the AHB and Header Endec (communication bus).
<R>
3.18.1 Features
- AHB latency: latency is 1 in read and write access (latency is 2 in read access following write access).
- Communication bus latency: latency is 1 in read and write access
- Arbitration of access when contention arises: Round robin
- AHB bus width: 32 bits
- Communication bus width: 128 bits
- RAM bus width: 128 bits (without ECC circuit)
- AHB transfer size: 8/16/ 32-bit selectable
- Communication bus transfer size: 8/16/32/128-bit selectable
- Burst transmission: single burst transfer, burst transfer of the required length, burst transfer of the fixed length
(INCR4/8/16, WRAP4/8/16)
- Little endian fixed
- ECC response: 1-bit error correction, 2-bit error detection <R>
R18DS0008EJ0401
Feb 28, 2017
Page 63 of 110