R-IN32M3 Datasheet, PDF (62/116 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
3. Specifications
3.17 Instruction RAM
The instruction RAM is 768 Kbytes of memory that can be accessed from I-code AHB, D-code AHB, DMAC or an
external MCU.
3.17.1 Features
- 128-bit (32-bit × 4) read buffer
- Latency: latency is 2 in read access in general but 1 in the case of hitting the read buffer.
latency is 1 in write access.
- AHB bus width: 32 bits
- RAM data bus width: 128 bits (without ECC circuit)
- Transfer size: 16- or 32-bit transfer selectable
- Burst transfer: single burst transfer, burst transfer of the required length, burst transfer of the fixed length
(INCR4/8/16, WRAP4/8/16)
- Little endian fixed
- ECC response: 1-bit error correction, 2-bit error detection <R>
3.17.2 Read Buffer
- 128-bit (32bit × 4) read buffer
- Response to the AHB involves no waiting in the case of hitting the read buffer
- Clear the data in the read buffer when a 2-bit ECC error occurs.
- A 2-bit ECC error at the time of the read response generates an ECC error interrupt. <R>
3.17.3 Write Interface
- When 16-bit write access arises, write to the RAM in 32-bit units through two consecutive rounds of access.
- When 8-bit write access arises, return an error response.
Caution: Write access by an external MCU in 16 bit units may occur. The specification assumes that
such access to the RAM will always proceed two consecutive times (for the writing of data
in 32-bit units).
R18DS0008EJ0401
Feb 28, 2017
Page 62 of 110