R-IN32M3 Datasheet, PDF (44/116 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
3. Specifications
3.1.2
CPU Core Configuration
The Cortex-M3 of an R-IN32M3 has the following configurations.
Category
Interrupts
Interrupt priority
MPU
Debug level
Trace level
SW/SWJ-DP
selection
Bit-band area
Configuration Item
NUM_IRQ
LVL_WIDTH
MPU_PRESENT
DEBUG_LVL
TRACE_LVL
JTAG_PRESENT
BB_PRESENT
Setting
128
4
Yes
3
2
SWJ-DP
Yes
Remark
The number of IRQ interrupts to be input: 1 to 240
(NMI interrupts are counted separately)
Priority bit number 3 to 8 (8 to 256 priority levels)
Presence of the memory protection unit
Debug level 1 to 3
Trace level 0 to 2
SWJ-DP is selected when JTAG access circuit is
built in.
Presence of bit-banding
Debug Level
Function outline
1
Minimum debug
configuration
Debugging halt
Breakpoints
Yes
2 (Instruction)
DWT comparator number
Flash patch function
1 (Data matching is not
available)
No
2
Full Debug configuration
(Data matching is not
available)
Yes
6 (Instruction)
2 (Literal)
4 (Data matching is not
available)
Yes
3 (Settings in R-IN32M3)
Full debug configuration
(with data matching)
Yes
6 (Instruction)
2 (Literal)
4
Yes
Trace Level
Function outline
ITM and TPIU functions
DWT trigger and counter
ETM function
0
No trace
No
No
No
1
Standard trace
Yes
Yes
No
2 (Settings in R-IN32M3)
Full trace
Yes
Yes
Yes
Caution: R-IN32M3 products do not support SLEEPDEEP mode. Do not set the SLEEPDEEP bit of the
SCR register to 1.
R18DS0008EJ0401
Feb 28, 2017
Page 44 of 110