R-IN32M3 Datasheet, PDF (60/116 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
3. Specifications
3.15 Asynchronous SRAM Memory Controller
The asynchronous SRAM memory controller is connectable to external paged ROM, ROM, and SRAM through a 16- or
32-bit bus. It is also connectable to peripheral devices compliant with the SRAM interface.
The pin functions for the asynchronous SRAM memory controller are multiplexed with those for the synchronous burst
access memory controller and the external MCU interface, and the asynchronous controller can be used when the low
level is applied to both the MEMCSEL and MEMIFSEL pins.
When both the BOOT0 and BOOT1 pins are at the low level, booting is from the memory connected to CSZ0.
3.15.1 Features
- Memory controller supporting page ROM, ROM, SRAM
- 32- or 16-bit data Bus
- Static memory control
 SRAM and I/O connection
 Page ROM connection (CSZ0 only)
 Four chip select signals are available (CSZ0-CSZ3)
CSZ0: page ROM / SRAM: 1000 0000H-13FF_FFFFH (64 Mbytes)
CSZ1: SRAM only: 1400 0000H-17FF_FFFFH (64 Mbytes)
CSZ2: SRAM only: 1800 0000H-1BFF_FFFFH (64 Mbytes)
CSZ3: SRAM only: 1C00 0000H-1FFF_FFFFH (64 Mbytes)
- Programmable wait
 Address setup wait
 Data wait
 Write recovery wait
 Idle wait <R>
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Feb 28, 2017
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