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R-IN32M3 Datasheet, PDF (78/116 Pages) Renesas Technology Corp – LSI for Industrial Ethernet | |||
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R-IN32M3 Series Data Sheet
(a) Read timing
4. Electrical Specifications
BUSCLK (output)
< tDKA >
A1-A26 (output)
< tDKA >
CSZ0-CSZ3 (output)
< tDKA >
WRZ0-WRZ3note, WRSTB (output)
< tDKWR >
BENZ0-BENZ3note (output)
< tDKRD >
RDZ (output)
< tHKOD >
D0-D31 (i/o)
WAITZ (input)
< tHKW >
< tSKW >
< tDKBS > < tDKBS >
BCYSTZ (input)
< tDKWR >
< tDKRD >
< tSKID >
< tHKID >
Figure 4.4 Memory Controller Read Timing Diagram (Asynchronous Memory)
Note: The WRZ0-WRZ3 pins function both as WRZ0-WRZ3 and BENZ0-BENZ3. These pins function as
BENZ0-BENZ3 after a reset and can be switched with the write enable switch registers (WREN).
For details, see section 9.3.5, Write Enable Switch Registers (WREN), in the R-IN32M3 Series
Userâs Manual: Peripheral Modules.
Remark: Above timing shows the case for when âIdle Waitâ, âWrite Recovery Waitâ, and âAddress
Waitâ are set to 0, and âData Waitâ is set to 3.
R18DS0008EJ0401
Feb 28, 2017
Page 78 of 110
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