R-IN32M3 Datasheet, PDF (49/116 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
3. Specifications
3.6 DMA Controller for Real-time Port
3.6.1
Features
- Number of channels: 1
- Transfer data size
 Independently selectable for source and destination
 Size range: 8 to 128 bits
- Maximum number of transfer bytes : 23²-1
- DMA transfer methods
 Register mode:
DMA transfer is performed according to the control register in the DMA controller that is set from the CPU. The
conventionally used General DMA transfer is supported.
Link mode :
DMA transfer is performed according to a descriptor located in data RAM and external memory. The
responsiveness of this mode is inferior to register mode because the access of the descriptor occurs at every DMA
transfer.
- SKIP function
A continuous access size and discrete access size can be set respectively for the area to be accessed for DMA transfer.
After space of the set continuous access size has been accessed, the function can skip space of the set discrete access
size before accessing the next address.
- Buffer data dump function
When DMA is forced to stop, the function can dump the data stored in the buffer. After the dump, the DMA transfer is
continued.
- Suspension function
The ongoing DMA transaction can be suspended.
- DMA transfers interval setting function
The DMA transfer interval can be specified to adjust the bus occupancy rate.
- Transfer mode
Single transfer mode
When a DMA transfer request is made, the right to use the bus is acquired and the bus is released each time a
transfer is completed. After that, whenever a DMA transfer request is made, this operation is repeated until the
numbers of transfers specified in the control register are completed.
Block transfer mode
When a DMA transfer request is made, the right to use the bus is acquired and data transfer is repeated until the
numbers of transfers specified in the control register are completed. In this case, the bus is not occupied.
Caution: Transfer 128-bit wide data requires the data to be aligned on a 128-bit boundary.
R18DS0008EJ0401
Feb 28, 2017
Page 49 of 110