R-IN32M3 Datasheet, PDF (52/116 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
3. Specifications
3.9 Asynchronous Serial Interface
3.9.1
Features
-Full-duplex communication via built-in receive and transmit FIFOs
Internal 10-bit × 16 receive data FIFO
Internal 8-bit × 16 transmit data FIFO
-2-pin configuration
Transmit data output pin
Receive data input pin
-Error detection functions
Rx parity error
Rx framing error
Tx data consistency error
-Tx FIFO overflow error
Rx FIFO overrun error
Rx timeout error
Rx BF receive error
-FIFO status information
Rx FIFO full/empty status
Tx FIFO empty/empty status
Rx FIFO fill level
Tx FIFO fill level
-Interrupt requests: 3
Transmission interrupt
Reception interrupt
Status interrupt
-Character length: 7 or 8 bits
-Parity options: odd, even, 0, none
-Transmission stop bits: 1 or 2 bits
-MSB-/LSB-first transfer selectable
-Transmit/receive data inverted input/output possible
-13 to 20 bits selectable for the BF (Break Field) in the LIN (Local Interconnect Network) communication format
Recognition of 11 bits or more possible for BF reception in LIN communication format
BF reception flag provided
-BF reception can be detected during data communication
-Bus monitor function to keep data consistency of the transmit data
-Supported Baud rate: 300 to 12,500,000bps
R18DS0008EJ0401
Feb 28, 2017
Page 52 of 110