HD64F3694FXV Datasheet, PDF (77/452 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be
input to this input pin.
• Prior to executing BCLR instruction
P57
P56
P55
Input/output Input Input Output
Pin state
Low
level
High
level
Low
level
PCR5
0
0
1
PDR5
1
0
0
P54
Output
Low
level
1
0
P53
Output
Low
level
1
0
P52
Output
Low
level
1
0
P51
Output
Low
level
1
0
P50
Output
Low
level
1
0
• BCLR instruction executed
BCLR #0, @PCR5
The BCLR instruction is executed for PCR5.
• After executing BCLR instruction
P57
P56
P55
Input/output Output Output Output
Pin state
Low
level
High
level
Low
level
PCR5
1
1
1
PDR5
1
0
0
P54
Output
Low
level
1
0
P53
Output
Low
level
1
0
P52
Output
Low
level
1
0
P51
Output
Low
level
1
0
P50
Input
High
level
0
0
• Description on operation
1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only
register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F.
2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE.
3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends.
As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However,
bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins.
To prevent this problem, store a copy of the PDR5 data in a work area in memory and
manipulate data of the bit in the work area, then write this data to PDR5.
Rev.5.00 Nov. 02, 2005 Page 47 of 418
REJ09B0028-0500