HD64F3694FXV Datasheet, PDF (314/452 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 EEPROM
Addresses in the page are incremented at each receipt of the write data and the write data can
be input up to 8 bytes. If the LSB 3 bits (A2 to A0) in the EEPROM address reach the last
address of the page, the address will roll over to the first address of the same page. When the
address is rolled over, write data is received twice or more to the same address, however, the
last received data is valid. At the receipt of the stop condition, write data reception is
terminated and the write operation is entered.
The page write operation is shown in figure 17.4.
SCL
SDA
1 2 34 5 6 7891
8 91
891
89
A15
A8
A7
A0
D7
D0
D7
D0
Start
condition
Slave address
R/W ACK
Upper memory
address
lower memory
ACK _address
ACK
Write Data
ACK
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read),
ACK: acknowledge
Figure 17.4 Page Write Operation
Write Data ACK
Stop
conditon
17.4.8 Acknowledge Polling
Acknowledge polling feature is used to show if the EEPROM is in an internally-timed write cycle
or not. This feature is initiated by the input of the 8-bit slave address + R/W code following the
start condition during an internally-timed write cycle. Acknowledge polling will operate R/W
code = "0". The ninth acknowledgement judges if the EEPROM is an internally-timed write cycle
or not. Acknowledgement "1" shows the EEPROM is in a internally-timed write cycle and
acknowledgement "0" shows the internally-timed write cycle has been completed. The
acknowledge polling starts to function after a write data is input, i.e., when the stop condition is
input.
Rev.5.00 Nov. 02, 2005 Page 284 of 418
REJ09B0028-0500