HD64F3694FXV Datasheet, PDF (283/452 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 I²C Bus Interface 2 (IIC2)
SCL
(Master output)
SDA
(Master output)
SCL
(Slave output)
SDA
(Slave output)
TDRE
TEND
TRS
ICDRT
ICDRS
ICDRR
User
processing
Slave transmit mode
9
1
2
3
4
5
6
7
8
9
A
A
Slave receive
mode
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data n
[3] Clear TEND
[4] Read ICDRR (dummy read) [5] Clear TDRE
after clearing TRS
Figure 15.10 Slave Transmit Mode Operation Timing (2)
15.4.5 Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, refer to
figures 15.11 and 15.12. The reception procedure and operations in slave receive mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the
read data show the slave address and R/W, it is not used.)
Rev.5.00 Nov. 02, 2005 Page 253 of 418
REJ09B0028-0500