HD64F3694FXV Datasheet, PDF (189/452 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 Timer W
Initial
Bit
Bit Name Value R/W Description
0
TOA
0
R/W Timer Output Level Setting A
Sets the output value of the FTIOA pin until the first
compare match A is generated.
0: Output value is 0*
1: Output value is 1*
Legend: X: Don't care.
Note: * The change of the setting is immediately reflected in the output value.
12.3.3 Timer Interrupt Enable Register W (TIERW)
TIERW controls the timer W interrupt request.
Initial
Bit
Bit Name Value
7
OVIE
0
6 to 4 
All 1
3
IMIED
0
2
IMIEC
0
1
IMIEB
0
0
IMIEA
0
R/W
R/W

R/W
R/W
R/W
R/W
Description
Timer Overflow Interrupt Enable
When this bit is set to 1, FOVI interrupt requested by OVF
flag in TSRW is enabled.
Reserved
These bits are always read as 1.
Input Capture/Compare Match Interrupt Enable D
When this bit is set to 1, IMID interrupt requested by
IMFD flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable C
When this bit is set to 1, IMIC interrupt requested by
IMFC flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable B
When this bit is set to 1, IMIB interrupt requested by
IMFB flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable A
When this bit is set to 1, IMIA interrupt requested by
IMFA flag in TSRW is enabled.
Rev.5.00 Nov. 02, 2005 Page 159 of 418
REJ09B0028-0500