HD64F3694FXV Datasheet, PDF (196/452 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 Timer W
TCNT value
H'FFFF
H'0000
Time
CTS bit
OVF
Flag cleared
by software
Figure 12.2 Free-Running Counter Operation
Periodic counting operation can be performed when GRA is set as an output compare register and
bit CCLR in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the
IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt
request is generated. TCNT continues counting from H'0000. Figure 12.3 shows periodic
counting.
TCNT value
GRA
H'0000
CTS bit
IMFA
Flag cleared
by software
Time
Figure 12.3 Periodic Counter Operation
By setting a general register as an output compare register, compare match A, B, C, or D can cause
the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to output 0, output 1, or toggle. Figure
12.4 shows an example of 0 and 1 output when TCNT operates as a free-running counter, 1 output
is selected for compare match A, and 0 output is selected for compare match B. When signal is
already at the selected output level, the signal level does not change at compare match.
Rev.5.00 Nov. 02, 2005 Page 166 of 418
REJ09B0028-0500