HD64F3694FXV Datasheet, PDF (303/452 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 16 A/D Converter
Table 16.3 A/D Conversion Time (Single Mode)
Item
Symbol Min
A/D conversion start delay time t
6
D
Input sampling time
t_SPL
—
A/D conversion time
t
CONV
131
Note: All values represent the number of states.
CKS = 0
Typ Max
—
9
31
—
—
134
CKS = 1
Min Typ Max
4
—
5
—
15
—
69
—
70
16.4.4 External Trigger Input Timing
A/D conversion can also be started by an external trigger input. When the TRGE bit in ADCR is
set to 1, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG input
pin sets the ADST bit in ADCSR to 1, starting A/D conversion. Other operations, in both single
and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 16.3
shows the timing.
φ
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 16.3 External Trigger Input Timing
Rev.5.00 Nov. 02, 2005 Page 273 of 418
REJ09B0028-0500