HD64F3694FXV Datasheet, PDF (443/452 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Item
Section 15 I²C Bus
Interface 2 (IIC2)
15.3.5 I²C Bus Status
Register (ICSR)
Page Revision (See Manual for Details)
242
Bit Bit Name
Description
3
STOP
Stop Condition Detection Flag
[Setting conditions]
• In master mode, when a stop condition is
detected after frame transfer
• In slave mode, when a stop condition is
detected after the general call address or
the first byte slave address, next to
detection of start condition, accords with
the address set in SAR
15.7 Usage Notes
264
Section 16 A/D Converter 268
16.3.1 A/D Data Registers
A to D (ADDRA to
ADDRD)
Section 18 Power-On
290
Reset and Low-Voltage
Detection Circuits
(Optional)
Figure 18.1 Block
Diagram of Power-On
Reset Circuit and Low-
Voltage Detection Circuit
Added
Therefore byte access to ADDR should be done by reading the
upper byte first then the lower one. Word access is also
possible. ADDR is initialized to H'0000.
RES
CRES
Section 21 Electrical
Characteristics
Table 21.2 DC
Characteristics (1)
318
Item
Applicable
Symbol Pins
Test Condition
Values
Min
Input high V_IH
voltage
Input low V_IL
voltage
PB0 to PB7 V_CC = 4.0 to 5.5 V V_CC × 0.7
RXD,SCL,
SDA,
P10 to P12,
:
P80 to P87
PB0 to PB7
V_CC = 4.0 to 5.5 V
V_CC × 0.8
–0.3
–0.3
Rev.5.00 Nov. 02, 2005 Page 413 of 418
REJ09B0028-0500