HD64F3694FXV Datasheet, PDF (294/452 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 I²C Bus Interface 2 (IIC2)
15.7 Usage Notes
15.7.1 Issue (Retransmission) of Start/Stop Conditions
In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing
under the following condition 1 or 2, such conditions may not be output successfully. To avoid
this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check
the SCLO bit in the I²C control register 2 (IICR2) to confirm the fall of the ninth clock.
1. When the rising of SCL falls behind the time specified in section 17.6, Bit Synchronous
Circuit, by the load of the SCL bus (load capacitance or pull-up resistance)
2. When the bit synchronous circuit is activated by extending the low period of eighth and ninth
clocks, that is driven by the slave device
15.7.2 WAIT Setting in I²C Bus Mode Register (ICMR)
If the WAIT bit is set to 1, and the SCL signal is driven low for two or more transfer clocks by the
slave device at the eighth and ninth clocks, the high period of ninth clock may be shortened. To
avoid this, set the WAIT bit in ICMR to 0.
Rev.5.00 Nov. 02, 2005 Page 264 of 418
REJ09B0028-0500