HD64F3694FXV Datasheet, PDF (17/452 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 I²C Bus Interface 2 (IIC2) ................................................................231
15.1 Features.............................................................................................................................. 231
15.2 Input/Output Pins ............................................................................................................... 233
15.3 Register Descriptions ......................................................................................................... 233
15.3.1 I²C Bus Control Register 1 (ICCR1)..................................................................... 234
15.3.2 I²C Bus Control Register 2 (ICCR2)..................................................................... 236
15.3.3 I²C Bus Mode Register (ICMR)............................................................................ 237
15.3.4 I²C Bus Interrupt Enable Register (ICIER) ........................................................... 239
15.3.5 I²C Bus Status Register (ICSR)............................................................................. 241
15.3.6 Slave Address Register (SAR).............................................................................. 244
15.3.7 I²C Bus Transmit Data Register (ICDRT)............................................................. 245
15.3.8 I²C Bus Receive Data Register (ICDRR).............................................................. 245
15.3.9 I²C Bus Shift Register (ICDRS)............................................................................ 245
15.4 Operation ........................................................................................................................... 246
15.4.1 I²C Bus Format...................................................................................................... 246
15.4.2 Master Transmit Operation ................................................................................... 247
15.4.3 Master Receive Operation..................................................................................... 249
15.4.4 Slave Transmit Operation ..................................................................................... 251
15.4.5 Slave Receive Operation....................................................................................... 253
15.4.6 Clocked Synchronous Serial Format..................................................................... 255
15.4.7 Noise Canceler...................................................................................................... 257
15.4.8 Example of Use..................................................................................................... 258
15.5 Interrupt Request................................................................................................................ 262
15.6 Bit Synchronous Circuit..................................................................................................... 263
15.7 Usage Notes ....................................................................................................................... 264
15.7.1 Issue (Retransmission) of Start/Stop Conditions .................................................. 264
15.7.2 WAIT Setting in I²C Bus Mode Register (ICMR) ................................................ 264
Section 16 A/D Converter..................................................................................265
16.1 Features.............................................................................................................................. 265
16.2 Input/Output Pins ............................................................................................................... 267
16.3 Register Descriptions ......................................................................................................... 268
16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 268
16.3.2 A/D Control/Status Register (ADCSR) ................................................................ 269
16.3.3 A/D Control Register (ADCR) ............................................................................. 270
16.4 Operation ........................................................................................................................... 271
16.4.1 Single Mode.......................................................................................................... 271
16.4.2 Scan Mode ............................................................................................................ 271
16.4.3 Input Sampling and A/D Conversion Time .......................................................... 272
16.4.4 External Trigger Input Timing.............................................................................. 273
Rev.5.00 Nov. 02, 2005 Page xv of xxviii