HD64F3694FXV Datasheet, PDF (281/452 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 I²C Bus Interface 2 (IIC2)
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
RDRF
9
1
2
3
4
5
6
7
8
9
A
A/A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RCVD
ICDRS Data n-1
Data n
ICDRR
User
processing
Data n-1
Data n
[5] Read ICDRR after setting RCVD
[7] Read ICDRR,
and clear RCVD
[6] Issue stop
condition _{[8] Set slave}
receive mode
Figure 15.8 Master Receive Mode Operation Timing (2)
15.4.4 Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,
refer to figures 15.9 and 15.10.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are
set to 1, and the mode changes to slave transmit mode automatically. The continuous
transmission is performed by writing transmit data to ICDRT every time TDRE is set.
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
with TDRE = 1. When TEND is set, clear TEND.
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.
5. Clear TDRE.
Rev.5.00 Nov. 02, 2005 Page 251 of 418
REJ09B0028-0500