HD64F3694FXV Datasheet, PDF (208/452 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 Timer W
12.5.7 Timing of IMFA to IMFD Setting at Input Capture
If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure
12.22 shows the timing of the IMFA to IMFD flag setting at input capture.
φ
Input capture
signal
TCNT
N
GRA to GRD
N
IMFA to IMFD
IRRTW
Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture
12.5.8 Timing of Status Flag Clearing
When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag
is cleared. Figure 12.23 shows the status flag clearing timing.
φ
Address
Write signal
TSRW write cycle
T1 T2
TSRW address
IMFA to IMFD
IRRTW
Figure 12.23 Timing of Status Flag Clearing by CPU
Rev.5.00 Nov. 02, 2005 Page 178 of 418
REJ09B0028-0500