HD64F3694FXV Datasheet, PDF (122/452 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 ROM
7.2.4 Flash Memory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. There are two modes: mode in which operation of the power supply
circuit of flash memory is partly halted in power-down mode and flash memory can be read, and
mode in which even if a transition is made to subactive mode, operation of the power supply
circuit of flash memory is retained and flash memory can be read.
Initial
Bit
Bit Name Value R/W Description
7
PDWND 0
R/W Power-Down Disable
When this bit is 0 and a transition is made to subactive
mode, the flash memory enters the power-down mode.
When this bit is 1, the flash memory remains in the
normal mode even after a transition is made to subactive
mode.
6 to 0 —
All 0
—
Reserved
These bits are always read as 0.
7.2.5 Flash Memory Enable Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers,
FLMCR1, FLMCR2, EBR1, and FLPWCR.
Initial
Bit
Bit Name Value R/W Description
7
FLSHE 0
R/W Flash Memory Control Register Enable
Flash memory control registers can be accessed when
this bit is set to 1. Flash memory control registers cannot
be accessed when this bit is set to 0.
6 to 0 —
All 0
—
Reserved
These bits are always read as 0.
Rev.5.00 Nov. 02, 2005 Page 92 of 418
REJ09B0028-0500