M3727GM6 Datasheet, PDF (71/129 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M3727GM6/M8–XXXSP/FP M37272E8SP/FP
Both HSYNC signal and VSYNC signal are negative-polarity input
HSYNC
Field
Field
determination
flag(Note)
Display dot line
selection bit
Display dot line
VSYNC and
(n -1) field
VSYNC
(Odd-numbered)
control
signal
T1
in microcom-
puter
Upper :
VSYNC signal
(n) field
(Even-numbered)
T2
Lower :
VSYNC control
signal in
micro-
computer
(n +1) field
(Odd-numbered)
T3
0.25 to 0.50[µs] at
f(XIN) = 8 MHz
Odd
0
Even 0 (T2 > T1)
1
0
Odd
1 (T3 < T2)
1
When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 0208 16) to “0.”
Dot line 1
Dot line 0
Dot line 0
Dot line 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
CC mode
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OSD mode
When the display dot line selection bit is “0,”
the “ ” font is displayed at even field, the
“ ” font is displayed at odd field. Bit 6 of the
I/O polarity control register can be read as the
field determination flag : “1” is read at odd field,
“0” is read at even field.
OSD ROM font configuration diagram
Note : The field determination flag changes at a rising edge of the V SYNC control signal (negative-polarity input) in
the microcomputer.
Fig. 8.11.14 Relation between Field Determination Flag and Display Font
Rev.1.00 Apr 01, 2001 page 71 of 127
REJ03B0132-0100Z