M3727GM6 Datasheet, PDF (68/129 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M3727GM6/M8–XXXSP/FP M37272E8SP/FP
8.11.2 Dot Size
The dot size can be selected by a block unit. The dot size in vertical
direction is determined by dividing HSYNC in the vertical dot size con-
trol circuit. The dot size in horizontal is determined by dividing the
following clock in the horizontal dot size control circuit : the clock
gained by dividing the OSD clock source (data slicer clock, OSC1) in
the pre-divide circuit. The clock cycle divided in the pre-divide circuit
is defined as 1TC.
The dot size of each block is specified by bits 2 to 4 of the block
control register i.
Refer to Figure 8.11.4 (the structure of the block control register).
The block diagram of dot size control circuit is shown in Figure 8.11.10.
OSC1
Data slicer clock
HSYNC
Synchronous
circuit
OC3 or OC4
“0”
Cycle ✕ 2
Clock cycle
= 1TC
“1” BCi4
Cycle ✕ 3
Pre-divide circuit
Horizontal dot size
control circuit
Vertical dot size
control circuit
OSD control circuit
Note: To use data slicer clock, set bit 0 of data slicer control register 1 to “1.”
Fig. 8.11.10 Block Diagram of Dot Size Control Circuit
1 dot
1TC
1TC
1/2H
1H
2TC
2H
3TC
3H
Scanning line of F1(F2)
Scanning line of F2(F1)
Fig. 8.11.11 Definition of Dot Sizes
Rev.1.00 Apr 01, 2001 page 68 of 127
REJ03B0132-0100Z