M3727GM6 Datasheet, PDF (49/129 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M3727GM6/M8–XXXSP/FP M37272E8SP/FP
8.10.1 Notes When not Using Data Slicer
When bit 0 of data slicer control register 1 (address 00E016) is “0,”
terminate the pins as shown in Figure 8.10.2.
<When data slicer circuit and timing signal generating circuit is in OFF state>
✽_{(Apply the same voltage as VCC to AVCC pin.)}
Leave HLF pin open.
Open
✽_(AVCC)
14
HLF
15
Leave VHOLD pin open.
Open ₁₆ VHOLD
Pull-down CV IN pin to VSS through
a resistor of 5 k Ω or more.
✽_{( ) ... M37272E8SP/FP}
5 kΩ or more
CVIN
17
Fig. 8.10.2 Termination of Data Slicer Input/Output Pins when Data Slicer Circuit and Timing Generating Circuit Is in OFF State
When both bits 0 and 2 of data slicer control register 1 (address
00E016) are “1,” terminate the pins as shown in Figure 8.10.3.
<When using a reference clock generated in timing signal generating circuit as OSD clock>
✽_{(Apply the same voltage as VCC to AVCC pin.)}
Connect the same external circuit as when
using data slicer to HLF pin.
1 µF
Leave VHOLD pin open.
1 kΩ
200pF
✽_(AVCC)
14
HLF
15
Open ₁₆ VHOLD
Pull-up CVIN to VCC through a resistor
of 5 kΩ or more.
✽_{( ) ... M37272E8SP/FP}
5 kΩ or more
CVIN
17
Fig. 8.10.3 Termination of Data Slicer Input/Output Pins when Timing Signal Generating Circuit Is in ON State
Rev.1.00 Apr 01, 2001 page 49 of 127
REJ03B0132-0100Z