M3727GM6 Datasheet, PDF (56/129 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M3727GM6/M8–XXXSP/FP M37272E8SP/FP
8.10.10 Data Clock Generating Circuit
This circuit generates a data clock synchronized with the start bit
detected in the start bit detecting circuit. The data clock stores cap-
tion data to the 16-bit shift register. When the 16-bit data has been
stored and the clock run-in determination circuit determines clock
run-in, the caption data latch completion flag is set. This flag is reset
at a falling of the vertical synchronous signal (Vsep).
Data Clock Position Register
b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 _{Data clock position register (DPS) [Address 00E516]}
B
Name
0 _{Fix this bit to “0.”}
1 Fix this bit to “1.”
2 Fix this bit to “0.”
3 Data clock position set
bits (DPS3 to DPS7)
4
to
7
Functions
After reset R W
1 _RW
0 RW
0 RW
1 RW
0
Fig. 8.10.11 Data Clock Position Register
Rev.1.00 Apr 01, 2001 page 56 of 127
REJ03B0132-0100Z