M3727GM6 Datasheet, PDF (70/129 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M3727GM6/M8–XXXSP/FP M37272E8SP/FP
8.11.4 Field Determination Display
To display the block with vertical dot size of 1/2H, whether an even
field or an odd field is determined through differences in a synchro-
nizing signal waveform of interlacing system. The dot line 0 or 1 (re-
fer to Figure 8.11.14) corresponding to the field is displayed alter-
nately.
In the following, the field determination standard for the case where
both the horizontal sync signal and the vertical sync signal are nega-
tive-polarity inputs will be explained. A field determination is deter-
mined by detecting the time from a falling edge of the horizontal sync
signal until a falling edge of the VSYNC control signal (refer to Figure
8.11.6) in the microcomputer and then comparing this time with the
time of the previous field. When the time is longer than the compar-
ing time, it is regarded as even field. When the time is shorter, it is
regarded as odd field
The contents of this field can be read out by the field determination
flag (bit 6 of the I/O polarity control register at address 00D816). A dot
line is specified by bit 5 of the I/O polarity control register (refer to
Figure 8.11.14).
However, the field determination flag read out from the CPU is fixed
to “0” at even field or “1” at odd field, regardless of bit 5.
I/O Polarity Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
I/O polarity control register (PC) [Address 00D8 16]
B
Name
0 HSYNC input polarity
switch bit (PC0)
1 VSYNC input polarity
switch bit (PC1)
2 R, G, B output polarity
switch bit (PC2)
3 OUT1 output polarity
switch bit (PC3)
4 OUT2 output polarity
switch bit (PC4)
5 Display dot line selection
bit (PC5) (See note)
6 Field determination flag
(PC6)
7 Fix this bit to “0.”
Functions
0 : Positive polarity input
1 : Negative polarity input
0 : Positive polarity input
1 : Negative polarity input
0 : Positive polarity output
1 : Negative polarity output
0 : Positive polarity output
1 : Negative polarity output
0 : Positive polarity output
1 : Negative polarity output
0 : “ ” at even field
“ ” at odd field
1 : “ ” at even field
“ ” at odd field
0 : Even field
1 : Odd field
After reset _{R W}
0 RW
0 RW
0 RW
0 RW
0 RW
0 RW
1 R—
0 RW
Note: Refer to the corresponding figure (8.11.14).
Fig. 8.11.13 I/O Polarity Control Register
Rev.1.00 Apr 01, 2001 page 70 of 127
REJ03B0132-0100Z