M3727GM6 Datasheet, PDF (7/129 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M3727GM6/M8–XXXSP/FP M37272E8SP/FP
7. PIN DESCRIPTION
Table 7.1 Pin Description
Pin
Name
VCC, (AVCC) Power source
VSS
CNVSS
______
RESET
CNVSS
Reset input
Input/
Output
Input
XIN
XOUT
Clock input
Clock output
Input
Output
P00/PWM0– I/O port P0
P05/PWM5,
P06/INT2/AD4,
P07/INT1 _{PWM output}
I/O
Output
External interrupt
input
Analog input
P10/OUT2, I/O port P1
P11/SCL1,
P12/SCL2, OSD output
P13/SDA1, Multi-master
P14/SDA2, ^{I2C-BUS interface}
P15/AD1/INT3, Analog input
P16/AD2, External interrupt
P17/AD3 ^input
P20/SCLK, I/O port P2
P21/SOUT,
P22/SIN, Serial I/O synchronous
P23/TIM3, clock input/output port
P24/TIM2, Serial I/O data
P25,
output
P26/OSC1/
XCIN,
P27/OSC2/
XCOUT
Serial I/O data input
External clock
input for timer
Clock input for OSD
Clock output for OSD
Input
Input
I/O
Output
I/O
Input
Input
I/O
I/O
I/O
Input
Input
Input
Output
Sub-clock input
Sub-clock output
Input
Output
Functions
Apply voltage of 5 V ± 10 % to (typical) VCC (AVCC), and 0 V to VSS.
( ) .. Only M37272E8SP/FP
This is connected to VSS.
To enter the reset state, the reset input pin must be kept at a LOW for 2 µs or more (under
normal VCC conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this LOW condition should
be maintained for the required time.
This chip has an internal clock generating circuit. To control generating frequency, an
external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and
XOUT. If an external clock is used, the clock source should be connected to the XIN pin and
the XOUT pin should be left open.
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually
programmed as input or output. At reset, this port is set to input mode. The output structure
is N-channel open-drain output. (See note 1)
Pins P00–P05 are also used as PWM output pins PWM0–PWM5 respectively. The output
structure is N-channel open-drain output.
Pins P06 and P07 are also used as INT external interrupt input pins INT2 and INT1 respectively.
P06 pin is also used as analog input pin AD4.
Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output. (See note 1)
Pins P10 is also used as OSD output pin OUT2. The output structure is CMOS output.
Pins P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master
I²C-BUS interface is used. The output structure is N-channel open-drain output.
Pins P10, P15–P17 are also used as analog input pin AD8, AD1–AD3 respectively.
P15 pin is also used as INT external interrupt input pin INT3.
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output. (See note 1)
P20 pin is also used as serial I/O synchronous clock input/output pin SCLK. The output
structure is N-channel open-drain output.
P21 pin is also used as serial I/O data output pin SOUT. The output structure is open-drain
output.
P22 pin is also used as serial I/O data input pin SIN.
Pins P23 and P24 are also used as timer external clock input pins TIM3 and TIM2
respectively.
P26 pin is also used as OSD clock input pin OSC1. (See note 2)
P27 pin is also used as OSD clock input pin OSC2. The output structure is CMOS output.
(See note 2)
P26 pin is also used as sub-clock input pin XCIN.
P27 pin is also used as sub-clock output pin XCOUT.
Rev.1.00 Apr 01, 2001 page 7 of 127
REJ03B0132-0100Z