M3727GM6 Datasheet, PDF (50/129 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M3727GM6/M8–XXXSP/FP M37272E8SP/FP
Figures 8.10.4 and 8.10.5 the data slicer control registers.
Data Slicer Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
01100
Data slicer control register 1(DSC1) [Address 00E016]
B
Name
Functions
0 Data slicer and timing signal
generating circuit control bit (DSC10)
1 Selection bit of data slice reference
voltage generating field (DSC11)
2 Reference clock source
selection bit (DSC12)
3, 4 Fix these bits to “0.”
0: Stopped
1: Operating
0: F2
1: F1
0: Video signal
1: HSYNC signal
After reset R W
0 RW
0 RW
0 RW
0 RW
5, 6 Fix these bits to “1.”
7 Fix this bit to “0.”
0 RW
0 RW
Definition of fields 1 (F1) and 2 (F2)
F1: Hsep
Vsep
F2: Hsep
Vsep
Fig. 8.10.4 Data Slicer Control Register 1
Data Slicer Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
1
Data slicer control register 2 (DSC2) [Address 00E116]
B
Name
0 Caption data latch
completion flag 1
(DSC20)
1 Fix this bit to “1.”
Functions
After reset R W
0: Data is not latched yet Indeterminate R —
and a clock-run-in is not
determined.
1: Data is latched and a
clock-run-in is determined.
0
RW
2 Test bit
Read-only
Indeterminate R —
3 Field determination
flag(DSC23)
0: F2
1: F1
4 Vertical synchronous signal 0: Method (1)
(Vsep) generating method
1: Method (2)
selection bit (DSC24)
5 V-pulse shape
0: Match
determination flag (DSC25) 1: Mismatch
6 Fix this bit to “o.”
7 Test bit
Read-only
Indeterminate R —
0
RW
Indeterminate R —
0
RW
Indeterminate R —
Definition of fields 1 (F1) and 2 (F2)
F1: Hsep
Vsep
F2: Hsep
Vsep
Fig. 8.10.5 Data Slicer Control Register 2
Rev.1.00 Apr 01, 2001 page 50 of 127
REJ03B0132-0100Z