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M3727GM6 Datasheet, PDF (19/129 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER | |||
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M3727GM6/M8âXXXSP/FP M37272E8SP/FP
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 00FC16]
B
Name
Functions
0 Timer 1 interrupt
0 : No interrupt request issued
request bit (TM1R) 1 : Interrupt request issued
1 Timer 2 interrupt
0 : No interrupt request issued
request bit (TM2R) 1 : Interrupt request issued
2 Timer 3 interrupt
0 : No interrupt request issued
request bit (TM3R) 1 : Interrupt request issued
3 Timer 4 interrupt
0 : No interrupt request issued
request bit (TM4R) 1 : Interrupt request issued
4 OSD interrupt request 0 : No interrupt request issued
bit (OSDR)
1 : Interrupt request issued
5 VSYNC interrupt
0 : No interrupt request issued
request bit (VSCR) 1 : Interrupt request issued
6 INT3 external interrupt 0 : No interrupt request issued
request bit (VSCR) 1 : Interrupt request issued
7 Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is â0.â
After reset R W
0 Râ½
0 Râ½
0 Râ½
0 Râ½
0 Râ½
0 Râ½
0 Râ½
0 Râ
â½: â0â can be set by software, but â1â cannot be set.
Fig. 8.3.2 Interrupt Request Register 1
Interrupt Request Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt request register 2 (IREQ2) [Address 00FD16]
B
Name
0 INT1 external interrupt
request bit (INIR)
1 Data slicer interrupt
request bit (DSR)
2 Serial I/O interrupt
request bit (S1R)
3 f(XIN)/4096 interrupt
request bit (CKR)
4 INT2 external interrupt
request bit (IN2R)
5 Multi-master I2C-BUS
interrupt request bit (IICR)
6 Timer 5 ⢠6 interrupt
request bit (TM56R)
7 Fix this bit to â0.â
Functions
After reset R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 Râ½
0 Râ½
0 Râ½
0 Râ½
0 Râ½
0 Râ½
0 : No interrupt request issued
1 : Interrupt request issued
0 Râ½
0 RW
â½: â0â can be set by software, but â1â cannot be set.
Fig. 8.3.3 Interrupt Request Register 2
Rev.1.00 Apr 01, 2001 page 19 of 127
REJ03B0132-0100Z
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