M3727GM6 Datasheet, PDF (47/129 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M3727GM6/M8–XXXSP/FP M37272E8SP/FP
8.9 ROM CORRECTION FUNCTION
This can correct program data in ROM. Up to 2 addresses can be
corrected, a program for correction is stored in the ROM correction
vector in RAM as the top address. The ROM correction vectors are 2
vectors.
Vector 1 : address 030016
Vector 2 : address 032016
Set the address of the ROM data to be corrected into the ROM cor-
rection address register. When the value of the counter matches the
ROM data address in the ROM correction vector as the top address,
the main program branches to the correction program stored in the
ROM memory for correction. To return from the correction program
to the main program, the op code and operand of the JMP instruction
(total of 3 bytes) are necessary at the end of the correction program.
The ROM correction function is controlled by the ROM correction
enable register.
Notes 1: S p e c i f y t h e f i r s t a d d r e s s ( o p c o d e a d d r e s s ) o f e a c h
instruction as the ROM correction address.
2: Use the JMP instruction (total of 3 bytes) to return from
the correction program to the main program.
3: Do not set the same ROM correction address to vectors 1
and 2.
ROM correction address 1 (high-order) 020A16
ROM correction address 1 (low-order) 020B16
ROM correction address 2 (high-order) 020C16
ROM correction address 2 (low-order) 020D16
Fig. 8.9.1 ROM Correction Address Registers
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
ROM correction enable register (RCR) [Address 020E 16]
B
Name
Functions
0 Vector 1 enable bit (RC0)
0: Disabled
1: Enabled
1 Vector 2 enable bit (RC1)
0: Disabled
1: Enabled
2 Nothing is assigned. These bits are write disable bits. When
to these bits are read out, the values are “0.”
7
After reset _{R W}
0 _RW
0 _RW
0 _R—
Fig. 8.9.2 ROM Correction Enable Register
Rev.1.00 Apr 01, 2001 page 47 of 127
REJ03B0132-0100Z