M32C82_15 Datasheet, PDF (70/84 Pages) Renesas Technology Corp – SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER

M32C/82 Group
5. Electrical Characteristics (VCC = 3.3 V)
Switching Characteristics
(VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85^oC unless otherwise specified)
VCC = 3.3V
Table 5.40 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory)
Symbol
Parameter
Measurement
condition
Standard
Unit
Min
Max
td(BCLK-AD) Address output delay time
18
ns
th(BCLK-AD) Address output hold time (BCLK standard)
0
ns
th(RD-AD) Address output hold time (RD standard)
0
ns
th(WR-AD) Address output hold time (WR standard)
(Note 1)
ns
td(BCLK-CS) Chip-select signal output delay time
18
ns
th(BCLK-CS) Chip-select signal output hold time (BCLK standard)
0
ns
th(RD-CS) Chip-select signal output hold time (RD standard)
0
ns
th(WR-CS) Chip-select signal output hold time (WR standard)
td(BCLK-ALE) ALE signal output delay time
See Figure 5.1 ^{(Note 1)}
ns
18
ns
th(BCLK-ALE) ALE signal output hold time
-2
ns
td(BCLK-RD) RD signal output delay time
th(BCLK-RD) RD signal output hold time
18
ns
-3
ns
td(BCLK-WR) WR signal output delay time
18
ns
td(BCLK-WR) WR signal outpu hold time
td(DB-WR) Data output delay time (WR standard)
0
ns
(Note 1)
ns
th(WR-DB)
tw(WR)
Data outpu hold time (WR standard)
Write pulse width
(Note 1)
ns
(Note 1)
ns
NOTES:
1. A value can be obtained from the following expressions according to the BCLK frequency.
td(DB – WR) =
th(WR – DB) =
10 ⁹ X n
– 20
f(BCLK)
10 ⁹
– 10
f(BCLK) X 2
[ns] (n=1 with 1 wait state, n=2 with 2 wait states
and n=3 with 3 wait states)
[ns]
th(WR – AD) =
10 ⁹
f(BCLK) X 2 ^{– 10 [ns]}
th(WR – CS) =
10 ⁹
f(BCLK) X 2 ^{– 10 [ns]}
tw( WR) =
10 ⁹ X n _{– 15 [ns] (n=1 with 1 wait state, n=3 with 2 wait states}
f(BCLK) X 2
and n=5 with 3 wait states)
Rev.1.20 Jun. 01, 2004 page 68 of 80