M32C82_15 Datasheet, PDF (25/84 Pages) Renesas Technology Corp – SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER

M32C/82 Group
2. Central Processing Unit (CPU)
2.1.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this
flag is set to "1".
2.1.8.6 Overflow Flag (O)
The O flag is set to "1" when a result of an arithmetic operation overflows; otherwise "0".
2.1.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to "0" and is enabled when the I flag is set to "1". The I
flag is set to "0" when an interrupt is acknowledged.
2.1.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1".
The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.1.8.9 Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide. It assigns an interrupt priority levels from level 0 to level 7.
If a requested interrupt has a greater priority than IPL, the interrupt is enabled.
2.1.8.10 Reserved Space
When writing to the reserved space, set to "0". When read, its content is indeterminate.
2.2 High-Speed Interrupt Registers
Registers associated with the high-speed interrupt are as follows.
- Flag save register (SVF)
- PC save register (SVP)
- Vector register (VCT)
2.3 DMAC-associated Registers
Registers associated with DMAC are as follows.
- DMA mode register (DMD0, DMD1)
- DMA transfer count register (DCT0, DCT1)
- DMA transfer count reload register (DRC0, DRC1)
- DMA memory address register (DMA0, DMA1)
- DMA SFR address register (DSA0, DSA1)
- DMA memory address reload register (DRA0, DRA1)
Rev.1.20 Jun. 01, 2004 page 23 of 80