M32C82_15 Datasheet, PDF (24/84 Pages) Renesas Technology Corp – SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER

M32C/82 Group
2. Central Processing Unit (CPU)
2.1 General Register
2.1.1 Data Registers (R0, R1, R2 and R3)
R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be
split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers.
R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R3R1.
2.1.2 Address Registers (A0 and A1)
A0 and A1 are 24-bit registers for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arith-
metic and logic operations.
2.1.3 Static Base Register (SB)
SB is a 24-bit register for SB-relative addressing.
2.1.4 Frame Base Register (FB)
FB is a 24-bit register for FB-relative addressing.
2.1.5 Program Counter (PC)
PC is 24 bits wide. It indicates an address of an instruction to be executed.
2.1.6 Interrupt Table Register (INTB)
INTB is a 24-bit register indicating a starting address of an interrupt vector table.
2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
USP and ISP as the stack pointer are 24 bits wide. The U flag can switch USP to ISP and vice versa.
Refer to "2.1.8 Flag Register (FLG)" about the U flag. Set USP and ISP to even addresses to execute an
interrupt sequence efficiently.
2.1.8 Flag Register (FLG)
FLG is a 16-bit register indicating a CPU state.
2.1.8.1 Carry Flag (C)
The C flag indicates whether carry or borrow occurs after an instruction is executed.
2.1.8.2 Debug Flag (D)
The D flag is for debug only. Set to "0".
2.1.8.3 Zero Flag (Z)
The Z flag is set to "1" when the value of zero is obtained from an arithmetic calculation; otherwise "0".
2.1.8.4 Sign Flag (S)
The S flag is set to "1" when a negative value is obtained from an arithmetic calculation; otherwise "0".
Rev.1.20 Jun. 01, 2004 page 22 of 80