M32C82_15 Datasheet, PDF (54/84 Pages) Renesas Technology Corp – SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER

M32C/82 Group
5. Electrical Characteristics (VCC = 5 V)
Switching Characteristics
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85^oC unless otherwise specified)
VCC = 5V
Table 5.22 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory and Selecting the DRAM Area)
Symbol
Parameter
Measurement
condition
Standard
Unit
Min
Max
td(BCLK-AD) Row address output delay time
18
ns
th(BCLK-AD) Row address output hold time (BCLK standard)
-3
ns
th(BCLK-CAD) Column address output delay time
18
ns
td(BCLK-CAD) Column address output hold time (BCLK standard)
-3
ns
th(RAS-RAD) Row address output hold time after RAS output
td(BCLK-RAS) RAS output delay time (BCLK standard)
(Note 1)
ns
18
ns
th(BCLK-RAS) RAS output hold time (BCLK standard)
tRP
RAS high ("H") hold time
See Figure 5.1 ^-3
ns
(Note 1)
ns
td(BCLK-CAS) CAS output delay time (BCLK standard)
th(BCLK-CAS) CAS output hold time (BCLK standard)
td(BCLK-DW) DW output delay time (BCLK standard)
th(BCLK-DW) DW output hold time (BCLK standard)
tsu(DB-CAS) CAS output setup time after DB output
18
ns
-3
ns
18
ns
-5
ns
(Note 1)
ns
th(BCLK-DB DB signal output hold time (BCLK standard)
tsu(CAS-RAS) CAS output setup time before RAS output (refresh)
-7
ns
(Note 1)
ns
NOTES:
1. A value can be obtained from the following expressions according to the BCLK frequency.
th(RAS – RAD) =
10 ⁹
– 13
[ns]
f(BCLK) X 2
tRP =
tsu(DB – CAS) =
10 ⁹
f(BCLK) X 2
X 3 – 20 [ns]
10 ⁹
– 20
[ns]
f(BCLK)
tsu(CAS – RAS) =
10⁹
– 13
[ns]
f(BCLK) X 2
Rev.1.20 Jun. 01, 2004 page 52 of 80