M32C82_15 Datasheet, PDF (51/84 Pages) Renesas Technology Corp – SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER

M32C/82 Group
5. Electrical Characteristics (VCC = 5 V)
Switching Characteristics
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85^oC unless otherwise specified)
VCC = 5V
Table 5.19 Memory Expansion Mode and Microprocessor Mode (with No Wait State)
Symbol
Parameter
Measurement
condition
Standard
Unit
Min
Max
td(BCLK-AD) Address output delay time
18
ns
th(BCLK-AD) Address output hold time (BCLK standard)
-3
ns
th(RD-AD) Address output hold time (RD standard)
0
ns
th(WR-AD) Address output hold time (WR standard)
(Note 1)
ns
td(BCLK-CS) Chip-select signal output delay time
18
ns
th(BCLK-CS) Chip-select signal output hold time (BCLK standard)
th(RD-CS) Chip-select signal output hold time (RD standard)
-3
ns
0
ns
th(WR-CS)
td(BCLK-ALE)
th(BCLK-ALE)
Chip-select signal output hold time (WR standard)
ALE signal output delay time
ALE signal output hold time
See Figure 5.1 ^{(Note 1)}
ns
18
ns
-2
ns
td(BCLK-RD)
th(BCLK-RD)
RD signal output delay time
RD signal output hold time
18
ns
-5
ns
td(BCLK-WR) WR signal output delay time
18
ns
td(BCLK-WR) WR signal outpu hold time
td(DB-WR) Data output delay time (WR standard)
-3
ns
(Note 1)
ns
th(WR-DB)
tw(WR)
Data outpu hold time (WR standard)
Write pulse width
(Note 1)
ns
(Note 1)
ns
NOTES:
1. A value can be obtained from the following expressions according to the BCLK frequency.
td(DB – WR) =
10 ⁹
f(BCLK)
– 20 [ns]
th(WR – DB) =
10 ⁹
– 10 [ns]
f(BCLK) X 2
th(WR – AD) =
10 ⁹
– 10 [ns]
f(BCLK) X 2
th(WR – CS) =
10 ⁹
– 10 [ns]
f(BCLK) X 2
tw(WR) =
10 ⁹
– 15 [ns]
f(BCLK) X 2
Rev.1.20 Jun. 01, 2004 page 49 of 80