M32C82_15 Datasheet, PDF (53/84 Pages) Renesas Technology Corp – SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER

M32C/82 Group
5. Electrical Characteristics (VCC = 5 V)
Switching Characteristics
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85^oC unless otherwise specified)
VCC = 5V
Table 5.21 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory and Selecting a Space with the
Multiplexed Bus)
Symbol
Parameter
Measurement
condition
Standard
Unit
Min
Max
td(BCLK-AD) Address output delay time
18
ns
th(BCLK-AD) Address output hold time (BCLK standard)
-3
ns
th(RD-AD) Address output hold time (RD standard)
(Note 1)
ns
th(WR-AD) Address output hold time (WR standard)
(Note 1)
ns
td(BCLK-CS) Chip-select signal output delay time
18
ns
th(BCLK-CS) Chip-select signal output hold time (BCLK standard)
th(RD-CS) Chip-select signal output hold time (RD standard)
-3
ns
(Note 1)
ns
th(WR-CS)
td(BCLK-RD)
th(BCLK-AD)
td(BCLK-WR)
td(BCLK-WR)
Chip-select signal output hold time (WR standard)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
(Note 1)
ns
See Figure 5.1
-5
18
ns
ns
18
ns
-3
ns
td(DB-WR)
th(WR-DB)
Data output delay time (WR standard)
Data output hold time (WR standard)
(Note 1)
ns
(Note 1)
ns
td(BCLK-ALE) ALE signal output delay time (BCLK standard)
th(BCLK-ALE) ALE signal output hold time (BCLK standard)
18
ns
-2
ns
td(AD-ALE)
th(ALE-AD)
tdz(RD-AD)
ALE signal output delay time (address standard)
ALE signal output hold time (address standard)
Address output high-impedance time
(Note 1)
ns
(Note 1)
ns
8
ns
NOTES:
1. A value can be obtained from the following expressions according to the BCLK frequency.
th(RD – AD) =
10 ⁹
f(BCLK) X 2 ^{– 10 [ns]}
th(WR – AD) =
10 ⁹
f(BCLK) X 2 ^{– 10 [ns]}
th(RD – CS) =
10 ⁹
f(BCLK) X 2 ^{– 10 [ns]}
th(WR – CS) =
10 ⁹
f(BCLK) X 2 ^{– 10 [ns]}
td(DB – WR) =
10⁹ X m
– 25
f(BCLK) X 2
[ns] (m=3 with 2 wait states and m=5 with 3 wait states)
th(WR – DB) =
10 ⁹
– 10 [ns]
f(BCLK) X 2
td(AD – ALE) =
10 ⁹
– 20
f(BCLK) X 2
[ns]
th(ALE – AD) =
10 ⁹
– 10 [ns]
f(BCLK) X 2
Rev.1.20 Jun. 01, 2004 page 51 of 80