M32C82_15 Datasheet, PDF (66/84 Pages) Renesas Technology Corp – SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER

M32C/82 Group
5. Electrical Characteristics (VCC = 3.3 V)
VCC = 3.3V
Timing Requirements (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85^oC unless otherwise specified)
Table 5.26 External Clock Input
Symbol
Parameter
tc
External clock input cycle time
tw(H)
External clock input high ("H") pulse width
tw(L)
External clock input low ("L") pulse width
tr
External clock rising-edge time
tf
External clock falling-edge time
Standard
Unit
Min
Max
50
ns
22
ns
22
ns
5
ns
5
ns
Table 5.27 Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Unit
Min Max
tac1(RD-DB) Data input access time (RD standard, with no wait state)
(Note 1) ns
tac1(AD-DB) Data input access time (AD standard, CS standard, with no wait state)
(Note 1) ns
tac2(RD-DB) Data input access time (RD standard, with a wait state)
(Note 1) ns
tac2(AD-DB) Data input access time (AD standard, CS standard, with a wait state)
(Note 1) ns
tac3(RD-DB) Data input access time (RD standard, when accessing a space with the multiplexed bus)
(Note 1) ns
tac3(AD-DB) Data input access time (AD standard, CS standard, when accessing a space with the multiplexed bus)
(Note 1) ns
tac4(RAS-DB) Data input access time (RAS standard, when accessing a DRAM space)
(Note 1) ns
tac4(CAS-DB) Data input access time (CAS standard, when accessing a DRAM space)
(Note 1) ns
tac4(CAD-DB) Data input access time (CAD standard, when accessing a DRAM space)
(Note 1) ns
tsu(DB-BCLK) Data input setup time
30
ns
tsu(RDY-BCLK) RDY input setup time
40
ns
tsu(HOLD-BCLK) HOLD input setup time
60
ns
th(RD-DB)
Data input hold time
0
ns
th(CAS-DB) Data input hold time
0
ns
th(BCLK-RDY) RDY input hold time
0
ns
th(BCLK-HOLD) HOLD input hold time
0
ns
td(BCLK-HLDA) HLDA output delay time
25 ns
NOTES:
1. A value can be obtained from the following expressions according to the BCLK frequecncy. Insert a wait state or use lower
f(BCLK) as an operation frequency if a calculated value is negative.
10 ⁹
tac1(RD – DB) = _{f(BCLK) X 2} – 35
[ns]
10 ⁹
tac1(AD – DB) = _f(BCLK)
– 35
[ns]
10 ⁹X m
tac2(RD – DB) = _{f(BCLK) X 2}
– 35
tac2(AD – DB) =
10⁹ X n
f(BCLK)
– 35
10⁹ X m
tac3(RD – DB) = _{f(BCLK) X 2}
– 35
tac3(AD – DB) =
10⁹ X n
f(BCLK) X 2
– 35
tac4(RAS – DB) =
10 ⁹X m
f(BCLK) X 2
– 35
tac4(CAS – DB) =
10⁹ X n
f(BCLK) X 2
– 35
tac4(CAD – DB) =
10 ⁹X l
f(BCLK)
– 35
[ns] (m=3 with 1 wait state, m=5 with 2 wait states
and m=7 with 3 wait states)
[ns] (n=2 with 1 wait state, n=3 with 2 wait states
and n=4 with 3 wait states)
[ns] (m=3 with 2 wait states and m=5 with 3 wait states)
[ns] (n=5 with 2 wait states and n=7 with 3 wait states)
[ns] (m=3 with 1 wait state and m=5 with 2 wait states)
[ns] (n=1 with 1 wait state and n=3 when 2 wait states)
[ns] (l=1 with 1 wait state and l=2 with 2 wait states)
Rev.1.20 Jun. 01, 2004 page 64 of 80