M32C82_15 Datasheet, PDF (57/84 Pages) Renesas Technology Corp – SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER

M32C/82 Group
5. Electrical Characteristics (VCC = 5V)
Vcc=5V
Memory expansion mode and microprocessor mode (with a wait state)
Read timing
BCLK
ALE
CSi
ADi
BHE
RD
18ns.max
td(BCLK-ALE) th(BCLK-ALE)
-2ns.min
td(BCLK-CS)
18ns.max⁽¹⁾
tcyc
td(BCLK-AD)
18ns.max⁽¹⁾
td(BCLK-RD)
18ns.max
tac2(RD-DB)⁽²⁾
tac2(AD-DB)⁽²⁾
th(BCLK-CS)
-3ns.min
th(RD-CS)
0ns.min
th(BCLK-AD)
-3ns.min
th(RD-AD)
0ns.min
th(BCLK-RD)
-5ns.min
DB
Hi-Z
tsu(DB-BCLK)
th(RD-DB)
26ns.min⁽¹⁾
0ns.min
Notes :
1. A value is guaranteed with no external factor. Maximum 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).
2. It varies with the operation frequency.
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states.)
tac2(AD-DB)=(tcyc x n-35)ns.max (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states.)
Write timing (written in 2 cycles with no wait state)
BCLK
ALE
CSi
ADi
BHE
WR,WRL,
WRH
18ns.max
td(BCLK-ALE)
th(BCLK-ALE)
-2ns.min
td(BCLK-CS)
18ns.max
tcyc
td(BCLK-AD)
18ns.max
th(BCLK-CS)
-3ns.min
th(WR-CS)⁽¹⁾
th(BCLK-AD)
-3ns.min
td(BCLK-WR)
18ns.max
tw(WR)⁽¹⁾
td(DB-WR)⁽¹⁾
th(WR-AD)⁽¹⁾
th(BCLK-WR)
-3ns.min
th(WR-DB)⁽¹⁾
DBi
NOTES:
1. It varies with the operation frequency.
td(DB-WR)=(tcyc x n-20)ns.min
(n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states)
th(WR-DB)=(tcyc/2-10)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2 x n-15)ns.min
(n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states)
Measurement conditions
• VCC=4.2 to 5.5V
• Input high and low voltage:
VIH=2.5V, VIL=0
• Output high and low voltage:
VOH=2.0V, VOL=0.8V
Figure 5.3 VCC=5V Timing Diagram (2)
Rev.1.20 Jun. 01, 2004 page 55 of 80