M32C82_15 Datasheet, PDF (19/84 Pages) Renesas Technology Corp – SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER

M32C/82 Group
1. Overview
Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued)
Symbol
Function I/O type
Description
P40 to P47
A16 to A22,
_____
A23
______
______
CS0 to CS3
I/O port P4
Address bus
Chip-select
I/O 8-bit I/O ports having equivalent functions to P0
______
O Outputs 8 high-order address bits (A16 to A22, A23).
______
The highest-order bit (A23) inversed is also output.
_______
_______
_______
_______
O Outputs CS0 to CS3 signals. CS0 to CS3 are chip-select signals specifying an
external space.
MA8 to MA12 Address bus
O Outputs row addresses and column addresses by time-sharing when accessing
the DRAM area.
P50 to P57
I/O port P5
I/O 8-bit I/O ports having equivalent functions to P0
CLKOUT
Clock output
O Outputs the main clock divided by 8 or divided by 32 or the clock having the
________
WRL
______
WR
_________
WRH
________
BHE
_____
RD
BCLK
__________
HLDA
__________
HOLD
ALE
________
RDY
Bus control pin
same frequency as the sub clock from P53.
________ _________ ______ ________ _____
_________
________
O Outputs WRL, WRH, (WR, BHE), RD, BCLK, HLDA and ALE signals. WRL
_________
_______
______
O and WRH or BHE and WR can be switched by program.
________ _________
_____
O
WRL, WRH and RD are selected
________
O The WRL signal becomes "L" by writing data to an even address in an external
O memory space.
_________
O The WRH signal becomes "L" by writing data to an odd address in an external
O memory space.
_____
I The RD pin signal becomes "L" by reading data in an external memory space.
______ ________
_____
O
WR, BHE and RD are selected
______
I The WR signal becomes "L" by writing data to an external memory space.
_____
The RD signal becomes "L" by reading data in an external memory space.
________
The BHE signal becomes "L" by accessing an odd address.
______ ________
_____
Select WR, BHE and RD for an external 8-bit data bus.
__________
While the HOLD pin is held "L", the microcomputer is placed in a hold state.
_________
In a hold state, HLDA outputs a "L" signal.
______
DW
_________
CASL
_________
CASH
_______
RAS
ALE is a signal latching the address.
________
While the RDY pin is held "L", the microcomputer is placed in a wait state.
______
DRAM bus control O The DW signal becomes "L" by writing data to the DRAM area.
_________
_________
pin
O CASL and CASH are signals indicating a timing to latch column addresses.
_________
O The CASL signal becomes "L" by accessing an even address.
__________
O The CASH signal becomes "L" by accessing an odd address.
_______
RAS is a signal latching row addresses.
P60 to P67
_________ _________
CTS0, CTS1
_________ _________
RTS0, RTS1
______ ______
SS0, SS1
I/O port P6
UART pin
I/O 8-bit I/O ports having equivalent functions to P0
I I/O pins for UART0 (P60 to P63) and UART1 (P64 to P67)
O
I
CLK0, CLK1
I/O
RxD0, RxD1
I
SCL0, SCL1
I/O
STxD0, STxD1
O
TxD0, TxD1
O
SDA0, SDA1
I/O
SRxD0, SRxD1
I
ISCLK2
Intelligent I/O pin I/O ISCKL2 inputs and outputs the clock for the intelligent I/O communication
OUTC21
O function.
OUTC21 outputs the clock for the waveform generating function.
I : Input O : Output I/O : Input and output
Rev.1.20 Jun. 01, 2004 page 17 of 80