4559 Datasheet, PDF (7/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4559 Group
DEFINITION OF CLOCK AND CYCLE
• Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
• Clock (f(XIN)) by the external ceramic resonator
• Clock (f(XIN)) by the external RC oscillation
• Clock (f(XIN)) by the external input
• Clock (f(RING)) of the on-chip oscillator which is the internal
oscillator
• Clock (f(XCIN)) by the external quartz-crystal oscillation
• System clock (STCK)
The system clock is the basic clock for controlling this product.
The system clock is selected by the clock control register MR
shown as the table below.
• Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
• Instruction clock (INSTCK)
The instruction clock is the basic clock for controlling CPU. The
instruction clock (INSTCK) is a signal derived by dividing the
system clock (STCK) by 3. The one instruction clock cycle
generates the one machine cycle.
Table 6 Table Selection of system clock
MR3
Register MR
MR2
MR1
MR0
System clock
1
1
0
0
f(STCK) = f(RING)/8
1
0
0
0
f(STCK) = f(RING)/4
0
1
0
0
f(STCK) = f(RING)/2
0
0
0
0
f(STCK) = f(RING)
1
1
0
1
f(STCK) = f(XIN)/8
1
0
0
1
f(STCK) = f(XIN)/4
0
1
0
1
f(STCK) = f(XIN)/2
0
0
0
1
f(STCK) = f(XIN)
1
1
1
0
f(STCK) = f(XCIN)/8
1
0
1
0
f(STCK) = f(XCIN)/4
0
1
1
0
f(STCK) = f(XCIN)/2
0
0
1
0
f(STCK) = f(XCIN)
Note 1. The f(RING)/8 is selected after system is released from reset
Operation mode
Internal frequency divided by 8 mode
Internal frequency divided by 4 mode
Internal frequency divided by 2 mode
Internal frequency through mode
High-speed frequency divided by 8 mode
High-speed frequency divided by 4 mode
High-speed frequency divided by 2 mode
High-speed through mode
Low-speed frequency divided by 8 mode
Low-speed frequency divided by 4 mode
Low-speed frequency divided by 2 mode
Low-speed through mode
Rev.1.04 Aug 23, 2007 Page 7 of 146
REJ03B0188-0104