4559 Datasheet, PDF (57/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4559 Group
High-speed mode
E
Clock operating mode
EPOF + POF instruction
execution
Key-on wakeup
Timer 3 underflow
(Stabilizing time c )
CRCK instruction no execution
B
Operation state
EPOF + POF 2 instruction
execution
Operation source clock: f(XIN)
Ceramic resonator
Key-on wakeup
(Stabilizing time c )
D
RAM back-up mode
EPOF + POF instruction
execution
Key-on wakeup
Timer 3 underflow
(Stabilizing time d )
CRCK instruction execution
C
Operation state
Operation source clock: f(XIN)
RC oscillation
MR1, MR0‹ 01
MR1, MR0‹ 00
Internal mode
EPOF + POF instruction
execution
(Stabilizing time a )
Key-on wakeup
Timer 3 underflow
(Stabilizing time b )
A
Operation state
Operation source clock:
f(RING)
On-chip oscillator
MR1, MR0 ‹ 10
Low-speed mode
MR1, MR0‹ 00
EPOF + POF 2 instruction
execution
Key-on wakeup
(Stabilizing time d )
EPOF + POF 2
instruction
execution
Key-on wakeup
(Stabilizing time b )
f(RING): stop
f(XIN): stop
f(XCIN): operating
EPOF + POF instruction
execution
Key-on wakeup
Timer 3 underflow
(Stabilizing time e )
D
Operation state
Operation source clock:
f(XCIN)
Quartz-crystal oscillation
EPOF + POF 2 instruction
execution
Key-on wakeup
(Stabilizing time e )
f(RING): stop
f(XIN): stop
f(XCIN): stop
Stabilizing time a : Microcomputer starts its operation after counting the f(RING) to 1376 times.
Stabilizing time b : Microcomputer starts its operation after counting the f(RING) to (system clock division ratio X 171) times.
Stabilizing time c : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio X 171) times.
Stabilizing time d : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio X 171) times.
Stabilizing time e : Microcomputer starts its operation after counting the f(XCIN) to (system clock division ratio X 171) times.
Notes 1: Selection of the system clock by the clock control registers MR and RG is state retained at power down.
The waiting time to stabilize oscillation at return can be adjustment by setting the clock control registers MR and RG
before transition to the power down state.
2: Continuous execution of the EPOF instruction and the POF instruction is required to go into the clock operating state.
3: Continuous execution of the EPOF instruction and the POF2 instruction is required to go into the RAM back-up state.
4: The state after system is released from reset;
• A ceramic resonator is selected as the main clock (f(XIN)).
• Main clock (f(XIN)) and Sub-clock (f(XCIN)) are valid.
5: When the RC oscillation circuit is used, executing the CRCK instruction is required.
If the CRCK instruction is not executed, the ceramic resonator is selected as the main clock f(XIN).
6: When the unoperating clock is selected as the system clock, turn it on by the clock control register RG,
and generate the wait time until the oscillation is stabilized, and then, switch the system clock.
7: The Sub-clock (quartz-crystal oscillation) is operating except in state D.
Fig 56. State transition
POF or
EPOF instruction + _POF2
instruction
Reset input
Power down flag P
S QP
R
POF or
Set source ^{• • • • • • •} EPOF instruction + POF2
instruction
Clear source• • • • • • System reset
Fig 57. Set source and clear source of the P flag
Rev.1.04 Aug 23, 2007 Page 57 of 146
REJ03B0188-0104
Program start
SNZP
instruction
P = “1”
?
No
Cold start
Yes
Warm start
T3F = “1”
Yes
?
No
SNZT3
instruction
Return from
timer 3 underflow
Return from
external wakeup signal
Fig 58. Start condition identified example using the
SNZP instruction