4559 Datasheet, PDF (33/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4559 Group
XCIN
ORCLK
W33
0
1
W32
Timer 3 (16)
1 - - 4 - - - - - 13 14 15 16
STCK
W42
0
1
W43
W31, W30
11
10
01
T3F ^{Timer 3}
interrupt
00
Timer 3 underflow signal
(T3UDF)
Timer LC (4)
Reload register RLC (4)
(TLCA)
(TLCA)
Register A
1/2
LCD
clock
INSTCK
Watchdog timer (16)
1 - - - - - - - - - - - - - 16
(Note 1)
SQ
WDF1
WRST instruction _R
Reset signal
(Note 3)
DWDT instruction
+
WRST instruction
SQ
WEF
R
(Note 2)
DQ
Watchdog reset
signal
T R ^{reset signal}
Data is set automatically from each reload register
when timer underflows (auto-reload function).
Note 1: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST instruction is executed
while flag WDF1 = “1”.
The WRST instruction is equivalent to the NOP instruction while flag WDF1 = “0”.
2: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and
WRST instruction are executed continuously.
3: The WEF flag is set to “1” at system reset or RAM back-up mode.
Fig 34. Timers structure (2)
Rev.1.04 Aug 23, 2007 Page 33 of 146
REJ03B0188-0104