4559 Datasheet, PDF (41/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4559 Group
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a
program run-away occurs. Watchdog timer consists of timer
WDT(16-bit binary counter), watchdog timer enable flag (WEF),
and watchdog timer flags (WDF1, WDF2).
The timer WDT downcounts the instruction clocks as the count
source from “FFFF16” after system is released from reset.
After the count is started, when the timer WDT underflow occurs
(after the count value of timer WDT reaches “000016,” the next
count pulse is input), the WDF1 flag is set to “1.” If the WRST
instruction is never executed until the timer WDT underflow
occurs (until timer WDT counts 65534), WDF2 flag is set to “1,”
and the RESET pin outputs “L” level to reset the microcomputer.
Execute the WRST instruction at each period of 65534 machine
cycle or less by software when using watchdog timer to keep the
microcomputer operating normally.
When the WEF flag is set to “1” after system is released from
reset, the watchdog timer function is valid.
When the DWDT instruction and the WRST instruction are
executed continuously, the WEF flag is cleared to “0” and the
watchdog timer function is invalid.
The WEF flag is set to “1” at system reset or RAM back-up
mode.
The WRST instruction has the skip function. When the WRST
instruction is executed while the WDF1 flag is “1”, the WDF1
flag is cleared to “0” and the next instruction is skipped.
When the WRST instruction is executed while the WDF1 flag is
“0”, the next instruction is not skipped.
The skip function of the WRST instruction can be used even
when the watchdog timer function is invalid.
FFFF16
Value of 16-bit timer (WDT)
000016
WDF1 flag
(2)
(2)
WDF2 flag
RESET pin output
65534 count
(Note) (4)
(1) Reset released
(3) WRST instruction
(5) System reset
executed (skip occurrence)
(1) After system is released from reset (= after program is started), timer WDT starts count down.
(2) When timer WDT underflow occurs, WDF1 flag is set to “1.”
(3) When the WRST instruction is executed while the WDF1 flag is “1”, WDF1 flag is cleared to “0,” the next
instruction is skipped.
(4) When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the watchdog reset
signal is output.
(5) The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is
executed.
Note: The number of count is equal to the number of machine cycle because the count source of watchdog timer
is the instruction clock.
Fig 40. Watchdog timer function
Rev.1.04 Aug 23, 2007 Page 41 of 146
REJ03B0188-0104