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4559 Datasheet, PDF (102/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
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4559 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SZC (Skip if Zero, Carry flag )
Instruc-
tion
code
D9
D0
0 0 0 0 1 0 1 1 1 1 2 0 2 F 16
Number of
words
1
Number of
cycles
1
Flag CY
-
Skip condition
(CY) = 0
Opera- (CY) = 0 ?
tion:
Grouping: Arithmetic operation
Description: Skips the next instruction when the contents of carry flag
CY is “0”.
After skipping, the CY flag remains unchanged.
Executes the next instruction when the contents of the CY
flag is “1”.
SZD (Skip if Zero, port D specified by register Y)
Instruc-
tion
code
D9
D0
0 0 0 0 1 0 0 1 0 0 2 0 2 4 16
Number of
words
2
Number of
cycles
2
Flag CY
-
Skip condition
(D(Y)) = 0
0 0 0 0 1 0 1 0 1 1 2 0 2 B 16 Grouping: Input/Output operation
Opera- (D(Y)) = 0 ?
tion: (Y) = 0 to 5
Description: Skips the next instruction when a bit of port D specified by
register Y is “0”. Executes the next instruction when the bit
is “1”.
Note:
(Y) = 0 to 5.
Do not execute this instruction if values except above are
set to register Y.
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
Instruc-
Number of Number of
tion
code
D9
D0
1 0 0 0 1 1 0 0 0 0 2 2 3 0 16
words
1
cycles
1
Flag CY
-
Skip condition
-
Opera-
tion:
(T17−T14) ← (B)
(R17−R14) ← (B)
(T13−T10) ← (A)
(R13−R10) ← (A)
Grouping: Timer operation
Description: Transfers the contents of register B to the high-order 4 bits
of timer 1 and timer 1 reload register R1. Transfers the
contents of register A to the low-order 4 bits of timer 1 and
timer 1 reload register R1.
T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B)
Instruc-
Number of Number of
tion
code
D9
D0
1 0 0 0 1 1 0 0 0 1 2 2 3 1 16
words
1
cycles
1
Flag CY
-
Skip condition
-
Opera-
tion:
(T27−T24) ← (B)
(R2L7−R2L4) ← (B)
(T23−T20) ← (A)
(R2L3−R2L0) ← (A)
Grouping: Timer operation
Description: Transfers the contents of register B to the high-order 4 bits
(T27−T24) of timer 2 and the high-order 4 bits (R2L7−R2L4)
of timer 2 reload register R2L. Transfers the contents of
register A to the low-order 4 bits (T23−T20) of timer 2 and
the low-order 4 bits (R2L3−R2L0) of timer 2 reload register
R2.
Rev.1.04 Aug 23, 2007 Page 102 of 146
REJ03B0188-0104
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