4559 Datasheet, PDF (53/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4559 Group
VOLTAGE DROP DETECTION CIRCUIT (WITH SKIP
JUDGMENT)
The built-in voltage drop detection circuit is used to set the
voltage drop detection circuit flag (VDF) or to perform system
reset.
EPOF instruction + POF instruction
EPOF instruction + POF2 instruction
Internal reset signal
Key-on wakeup signal
Timer 3 underflow signal
SQ
R
SVDE instruction S Q
Internal reset signal R
VDCE
(Note 2)
(Note 1)
(Note 1)
VDD
−
VSKIP
+
Flag occurrence
VDD
−
VRST^-/VRST⁺
+
Reset occurrence
Voltage drop
detection circuit
Voltage drop
detection circuit flag
VDF
Skip judgement
(SNZVD
instruction)
Voltage drop
detection circuit
reset signal
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
Fig 53. Voltage drop detection reset circuit
(1) Operating state of voltage drop detection circuit
The voltage drop detection circuit becomes valid by inputting
“H” to the VDCE pin and it becomes invalid by inputting “L.”
When not executing the SVDE instruction under “H” level of the
VDCE pin, the voltage drop detection circuit become invalid in
power down state (RAM back-up, clock operating mode). As for
this, the voltage drop detection circuit becomes valid at returning
from power down, again.
When executing the SVDE instruction under “H” level of the
VDCE pin, the voltage drop detection circuit becomes valid in
power down state (RAM back-up, clock operating mode).
The state of executing SVDE instruction can be cleared by
system reset.
Table 22 Operating state of voltage drop detection circuit
VDCE pin SVDE instruction
at CPU operating
No execute
×
“L”
Execute
×
No execute
O
“H”
Execute
O
Note. “O” indicates valid, “×” indicates invalid.
at power down
×
×
×
O
Rev.1.04 Aug 23, 2007 Page 53 of 146
REJ03B0188-0104