4559 Datasheet, PDF (49/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4559 Group
RESET FUNCTION
System reset is performed by the followings:
• “L” level is applied to the RESET pin externally,
• System reset instruction (SRST) is executed,
• Reset occurs by watchdog timer,
• Reset occurs by built-in power-on reset
• Reset occurs by voltage drop detection circuit
Then when “H” level is applied to RESET pin, software starts
from address 0 in page 0.
(1) RESET pin input
System reset is performed certainly by applying “L” level to
RESET pin for 1 machine cycle or more when the following
condition is satisfied;
the value of supply voltage is the minimum value or more of the
recommended operating conditions.
(Note 1)
RESET pin
(Note 2)
(Note 1)
Pull-up transistor
Internal reset signal
Voltage drop detection circuit
Power-on reset circuit
SRST instruction
Watchdog reset signal
WEF
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
Fig 48. Structure of RESET pin and its peripherals
Reset input
1 machine cycle or more
RESET
0.3VDD
(Note 1)
0.85VDD
Program starts
(address 0 in page 0)
f(RING)
On-chip oscillator (internal oscillator) is counted 1376
times (Note 2).
Notes 1: Keep the value of supply voltage to the minimum value or more of the
recommended operating conditions.
2: It depends on the internal state at reset.
Fig 49. RESET pin input waveform and reset release timing
Rev.1.04 Aug 23, 2007 Page 49 of 146
REJ03B0188-0104